Based on the survey conducted by this invention, there is no existing electrical test structure up to date known to effectively and rapidly detect the extend of overetch on source/drain silicide layer during the contact opening. Presently, the only feasible method is to use scanner electronic microscope (SEM) or blank test wafer in simulating chip processing. However, SEM method is not precise enough, destructive and time consuming, making wafer-mapping rather difficult. Furthermore, the blank test wafer method not only requires additional test wafer and production procedures, substituting the actual wafer with a blank one can easily produce considerable error.